1. Field of the Invention
The present invention relates to a method of wiring logic devices of a semiconductor integrated circuit, to provide a required operation, and particularly, to a method of wiring a semiconductor integrated circuit, capable of properly adjusting a delay in transmitting signals in the circuit.
2. Description of the Prior Art
A semiconductor integrated circuit has logic devices formed on a semiconductor substrate. The logic devices are wired with metal thin films, to provide a required operation. The wiring has resistance and capacitance that cause a delay in transmitting signals. This may disturb the timing of each signal, thereby causing trouble in the operation of the circuit.
Signals in an integrated circuit are classified into data bus signals and clock signals. The data bus signals are restricted by setup and hold time, and when transferred between registers, they must keep upper and lower limits on a delay, or they will not be transferred in time.
The clock signals must keep an upper limit for a skew, or devices such as flip-flops that are required to operate simultaneously will operate out of pace, to incorrectly transmit data. The clock signals must also keep upper and lower limits on a delay in a chip, or the chip in question will cause a skew with respect to another chip, thereby malfunctioning a system that contains the chips.
To minimize delay and skew due to the resistance and capacitance of wiring, several techniques such as Japanese Unexamined Patent Publications 4-0269860, 5-54100, and 6114951 have been proposed.
Recent semiconductor integrated circuits employ very fine wiring with small vias whose resistance causes a delay in transmitting signals.
The via is the interconnection between two layers having through-holes and rectangle pattern of the connection layers.
A fine via has a very small through-hole, which is very difficult to fill with conventional wiring material such as aluminum. In this case, the through-hole is filled with a different wiring material, which may increase the resistance of the via to a level which cannot be ignored.
A latest processing technique forms a gate length of 0.5 micrometers or shorter for a transistor. If tungsten (W) is used to fill a through-hole of a via formed according to such fine processing technique, the resistance of the through-hole becomes several ohms.
It is important to minimize delay and skew caused by the resistance of vias.
To reduce the resistance of a via, Japanese Unexamined Patent Publication 2-140952 discloses a technique to adjust the number of through-holes formed in a via, thereby providing a required current value. This technique, however, does not consider a delay caused by the resistance of the via itself when adjusting the number of through-holes.
The prior art deals only with a delay caused by the resistance and capacitance of wiring and provides no effective measures to deal with a delay caused by the resistance of vias.
There is no prior art that minimizes delay and skew caused by the resistance of vias and solves the problem in the recent fine wiring process.